CMOS pixels comprising epitaxial layers for light-sensing and light emission

ABSTRACT

Photonic devices monolithically integrated with CMOS are disclosed, including sub-100 nm CMOS, with active layers comprising acceleration regions, light emission and absorption layers, and optional energy filtering regions. Light emission or absorption is controlled by an applied voltage to deposited films on a pre-defined CMOS active area of a substrate, such as bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, Thin-Film GOI.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. Ser. No. 11/572,519 filed Jan. 23, 2007, now U.S. Pat. No. 8,963,169 issued Feb. 24, 2015, which is a 371 National Phase Application of PCT/EP05/008213 filed Jul. 28, 2005, claiming the benefit of U.S. Ser. No. 60/591,658 filed Jul. 28, 2004 and are hereby incorporated by reference herein in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates to light emission from semiconductor junctions in general, and in particular when those junctions are operated in the avalanche mode, as the active regions of Avalanche Light Emitting Diodes (ALEDs), thereby enabling light emission from indirect bandgap materials. It relates to the design of device layers and layout, as well as the method of fabrication, suitable for monolithic integration of ALEDs with sub-micron and sub-100 nm CMOS technologies, forming “Light Emitting Elements” (hereafter referred to as LIXELs). LIXELs can be implemented with Silicon bulk substrates, Thick-Film SOI substrates, or ultra-thin-film Silicon-On-Insulator (SOI) substrates, as well as with Germanium bulk substrates or ultra-thin-film Germanium-On-Insulator (GOI) substrates. Thin-Film GOI substrates are good candidates to be the used for sub-45 nm CMOS technology.

In the early years of semiconductor technology, it was noticed that silicon junctions operated in the avalanche mode emit white light. In fact it seems that light emission takes place across a large region of the electromagnetic spectrum, from the Long Wavelength Infra-Red (LWIR) to the Ultra-Violet (UV). Such wide interval of photon energies is an indication that different physical mechanisms, with different probabilities and efficiencies, are responsible for the emission of photons. Recent reviews of this topic can be found in: N. Akil, S. E. Kerns, D. V. Kerns, Jr., A. Hoffmann, J.-P. Charles, “A Multimechanism Model for Photon Generation by Silicon Junctions in Avalanche Breakdown”, IEEE Trans. on Elect. Dev., Vol. 46, No. 5, May 1999, pp. 10221028, and M. de la Bardonnie, D. Jiang, S. E. Kerns, D. V. Kerns, Jr., P. Mialhe, J.-P. Charles, A. Hoffman, “On the Aging of Avalanche Light Emission from Silicon Junctions”, IEEE Trans. on Elect. Dev., Vol. 46, No. 6, June 1999, pp. 1234-1239.

It is thought that some of those mechanisms are: (1) Interband transitions between (1a) hot electrons and thermal holes, (1b) hot holes and thermal electrons, (1c) hot electrons and hot holes; (2) Intraband transitions, (2a) in the conduction band, and/or (2b) in the valence band; (3) Brehmstrahlung due to scattering of hot carriers by ionized impurities.

Even though there has been ample experimental evidence since the 1950's that silicon can emit light, the efficiency has always been very low: roughly only 1 in 10⁷ recombinations across the bandgap emit light. This low efficiency is tied to the details of the band structure of silicon, namely the smallest bandgap is indirect at 1.1 eV, to device design/geometry, and to process architecture.

Conventional avalanche light emitting devices are made by ion implantation into a bulk substrate, to make either lateral or vertical pn-junctions. In either case, the location which emits light can be hundreds of nanometers away from the substrate surface, and consequently photons with energy larger than the minimum bandgap of the substrate are absorbed, thereby severely reducing the external power efficiency.

For all the reasons mentioned above, band-structure, device design, and process architecture, it has been impossible to take advantage for practical applications, of light emission from silicon junctions operated in the avalanche mode. On the other hand, conventional CMOS technology is not amenable to the integration of other semiconductor materials for the purpose of bandgap engineering of pn-junctions. For this reason full monolithic integration of efficient light emitting devices with CMOS has not been possible.

The present invention, based on the device and process architectures disclosed in WO 2002/33755, and in WO 2004/027879, and the new layout designs disclosed in a co-pending application, presents a new method of fabrication, device layers, and layout designs that enable the monolithic integration of ALEDs with advanced CMOS, including sub-100 nm technologies, in which the light emitting regions can be made of materials other than the semiconductor substrate (e.g., silicon or germanium). It also discloses optimized doping and heterojunction profiles for the purpose of increased efficiency of light emission, as well as optimized profiles for the purpose of light emission in certain ranges of wavelengths, namely in the 1.3 μm and 1.55 μm ranges.

The monolithic integration of ALEDs with advanced CMOS technology, in one exemplary implementation, requires only three additional masks, with respect to the number of masks required for the CMOS technology in question. It has been experimentally verified that the avalanche photo-diodes described in WO 2002/33755 and WO 2004/027879, with one of the layouts described in co-pending application, do emit light under certain conditions of operation.

SUMMARY OF THE INVENTION

An object of the present invention is a new process architecture for the fabrication of photonic devices, that is compatible with sub-micron and sub-100 nm CMOS technologies and improves the intrinsic and extrinsic efficiencies of light emission by avalanching junctions.

1. Substrate can be Si bulk or SOI, Ge bulk or GOI, SiGe virtual substrates—on bulk silicon or on insulator, etc. The type of substrate to be used is related to the requirements of the CMOS technology with which the device is to be monolithically integrated. 2. For films deposited on bulk substrates, the acceleration region (region of high electric field) can be located inside the substrate. In this case, the deposited film may include only the impact ionization region, or it may also include a region for “energy filtering”. 3. In the deposited film, the region designed to maximize impact ionization, may have n-type or p-type conductivity. 4. For films deposited on thin-film or ultra-thin-film SOI or GOI substrates, the doping and heterojunction profiles of the deposited films can be optimized for front-side light emission, or for back-side light emission, or for both. 5. For front-side light emission from films deposited on thin-film or ultra-thin-film SOI or GOI substrates, the films incorporate the “acceleration region”, optionally an energy filtering region, the region in which light emission is to take place, which is at the same time an electrode. 6. For back-side light emission from films deposited on thin-film or ultra-thin-film SOI or GOI substrates, the films incorporate the optional energy filtering region, the acceleration region and the electrode opposite to the one in which light emission takes place. 7. For front-side and back-side light emission from films deposited on thin-film or ultra-thin-film SOI or GOI substrates, the films incorporate the acceleration region, and the top electrode. The top and bottom electrodes must be suitable for light emission, and the acceleration region must be suitable for light emission on both of its ends. Optional energy filtering regions may be placed at both ends of the acceleration region, or just at one end. 8. Regardless of substrate used, the acceleration region should be mono-crystalline, because charge carrier mobility should be as high as possible. 9. Regardless of substrate used, the region in which light emission takes place should be as thin as possible to minimize lateral light emission through the side walls. 10. The region in which light emission takes place can be bandgap engineered so that the photon energy of the emitted light can be below the threshold for interband absorption in the substrate.

Another object of the present invention is a new device architecture, compatible with sub-micron and sub-100 nm CMOS technologies, that improve the intrinsic and extrinsic efficiencies of light emission by avalanching junctions.

1. The region in which light emission by avalanching takes place is a thin-film, deposited on an active area.

2. Electric field and avalanche current, are perpendicular to substrate surface;

3. The deposited film in which light emission by avalanching takes place, can be a pure material, a random alloy, or a short-period superlattice.

4. The deposition of the light emitting film can be engineered to form pseudomorphic crystalline films, poly-crystalline films, or amorphous films. It is also possible to have a combination of films of different materials. For example, pseudomorphic crystalline followed by poly-crystalline, or pseudomorphic crystalline followed by amorphous, or pseudomorphic crystalline followed by poly-crystalline, followed by amorphous. In addition, it is also possible to deposit a crystalline film and subsequently, with suitable processing, make it nano-crystalline or porous. 5. During the deposition process, the heterojunction and doping profiles can be optimized, for one or more of the physical mechanisms involved in light emission, in order to maximize the intrinsic efficiency of the light emission process(es). 6. The heterojunction and doping profiles of the deposited film(s) can be optimized for efficient light emission in a particular range of wavelengths. 7. The heterojunction and doping profiles of the deposited film(s) can be designed such that the deposited film is only used as the location for impact ionization. 8. The heterojunction and doping profiles of the deposited film(s), in addition to the location for impact ionization, can also incorporate regions that act as “energy filters”, that is, regions which allow charge carriers with only a certain energy range, to move to the region in which impact ionization (i.e. avalanching) takes place. 9. The heterojunction and doping profiles of the deposited film, in addition to the location for impact ionization, can also incorporate the regions in which the charge carriers are accelerated. 10. The heterojunction and doping profiles of the deposited film, in addition to the location for impact ionization, can incorporate regions that act as “energy filters”, and also incorporate the regions in which the charge carriers are accelerated. 11. The same device, when biased above the break-down voltage emits light, and when biased below the breakdown voltage, can operate as an avalanche photo-diode.

Yet another object of the present invention is a new layout architecture, compatible with sub-micron and sub-100 nm CMOS technologies, that improve the intrinsic and extrinsic efficiencies of light emission by avalanching junctions.

1. For monolithic integration in a BiCMOS process with a vertical Bipolar device, typical of SiGe (or SiGeC) BiCMOS process technologies, the active area for the light emitter can be either a CMOS active area or a Bipolar active area.

2. For monolithic integration in a pure CMOS process, the active area is a standard CMOS active area.

3. For monolithic integration with a pure CMOS process on bulk wafers, or thick-film SOI wafers, a conductive path to the bottom electrode of the light-emitting device is implemented with a well implant.

3a. For a p-type deposited film, the active area is n-type on a p-substrate. A conductive path to the n-type active area is implemented with a n-Well implant that overlaps both sides of a portion of the shallow trench isolation surrounding the n-type active area. 3b. For a n-type deposited film, the active area is p-type, on a n-substrate, or n-Well on a triple-well on p-substrate technology. A conductive path to the p-type active area is implemented with a p-Well implant that overlaps both sides of the shallow trench isolation surrounding the p-type active area. 3c. With n-type active areas, the n-Well implant can also overlap the source/drain region of a N-MOSFET on an adjacent active area, thereby providing an extremely compact arrangement of the light emitting device coupled to a switching element. 3d. With p-type active areas, the p-Well implant can also overlap the source/drain region of a P-MOSFET on an adjacent active area, thereby providing an extremely compact arrangement of the light emitting device coupled to a switching element. 4. For monolithic integration with pure CMOS process on thin-film SOI or GOI substrates, a lateral contact to the bottom electrode is provided by not fully encircling the active area with isolation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A presents a configuration of a device having a photonic device integrated with an N-MOSFET.

FIG. 1B illustrates another embodiment of a device having a photonic device integrated with an N-MOSFET and.

FIG. 1C illustrates another embodiment of a device having a photonic device integrated with an N-MOSFET.

FIG. 2A presents a configuration of a device having a photonic device without CMOS devices.

FIG. 2B shows another embodiment of a device having a photonic device without CMOS devices.

FIG. 2C shows another embodiment of a device having a photonic device without CMOS devices.

FIG. 3B presents a configuration of a device having a photonic device integrated with an N-MOSFET.

FIG. 3A presents another embodiment of a device having a photonic device integrated with an N-MOSFET.

FIG. 3D presents another embodiment of a device having a photonic device integrated with an N-MOSFET.

FIG. 3C presents another embodiment of a device having a photonic device integrated with an N-MOSFET.

FIG. 4B presents a configuration of a device having a photonic device without CMOS devices and a photonic device.

FIG. 4A presents another embodiment of a device having a photonic device without CMOS devices.

FIG. 4D presents another embodiment of a device having a photonic device without CMOS devices.

FIG. 4C presents another embodiment of a device having a photonic device without CMOS devices.

FIG. 4D presents another embodiment of a device having a photonic device without CMOS devices.

FIG. 5 shows an exemplary qualitative band diagram of a device with a p-type silicon bottom electrode, an undoped silicon “Accelerator” region, and n-type doped Ge layer, capped by a thin silicon layer, also n-type doped.

FIG. 6 shows an exemplary qualitative band diagram of a device with a p-type silicon bottom electrode, an undoped silicon “Accelerator” region, and n-type doped (SiC)—(GeC) superlattice layers, capped by a thin silicon layer, also n-type doped.

FIG. 7A shows a qualitative band diagram of a photonic device.

FIG. 8 shows an exemplary qualitative band diagram of a device under forward bias.

FIGS. 9A to 9H show the most relevant steps/modules of Process Flow #1. The devices of FIGS. 9A to 9H are meant to have a direct bandgap n-type layer, because the recombinations in those layers are between thermal electrons and thermal holes.

FIGS. 10A to 10E show the most relevant steps/modules of Process Flow #2.

FIGS. 11A to 11F show the most relevant steps/modules of Process Flow #3.

FIGS. 12A to 12G show the most relevant steps/modules of Process Flow #4.

DETAILED DESCRIPTION OF THE INVENTION

1. Method of Fabrication

The present invention makes use of the fabrication architecture and process flows disclosed in WO 2002/33755 which covers the fabrication of Avalanche Photo-Diodes (APDs) with epitaxially grown active layers, monolithically integrated with bulk CMOS devices. The fundamental advantage of that fabrication architecture is that some of the active layers of the APDs are epitaxially deposited on CMOS active areas, immediately adjacent to MOSFETs, thereby resulting in a very compact monolithic integration with CMOS. Because some of the active layers are epitaxial layers deposited on a silicon surface (active area), it is possible to have materials that are epitaxially compatible with silicon, other than silicon itself.

Similarly to WO2002/33755 and WO2004/027879, the method of fabrication of the present invention, follows the standard CMOS process flow until the formation of silicide layers. Ideally the epitaxial deposition takes place after all high temperature steps, such as the ion implantation and annealing of the source/drain CMOS junctions, have already taken place, so that the “as deposited” heterojunction and doping profiles are not modified by temperature induced diffusion and/or strain relaxation. In sub-100 nm CMOS, the subsequent processing steps, such as the silicide formation, as well as all metallization steps, can be performed at temperatures lower than those used for the epitaxial growth.

The method of fabrication of the present invention enables a very compact monolithic integration of APDs/ALEDs with advanced CMOS to form an “Active Matrix” of Pixels/Lixels, in which the APDs/ALEDs comprise epitaxially grown active layers with sophisticated doping and heterojunction profile engineering. This permits the fabrication of active regions with profoundly modified band structure, resulting in greatly improved optoelectronic characteristics with respect to the substrate (silicon or germanium, or a relaxed SiGe buffer layer). It must be emphasized that such sophisticated doping and heterojunction profile engineering are impossible with devices made without the epitaxial growth of those layers.

WO2002/33755 provides the method of fabrication on bulk substrates and thick-film SOI. WO2004/027879 provided the method of fabrication on thin-film SOI or GOI substrates, for front and/or back-side illumination. The present disclosure is applicable to bulk, thick-film and thin-film SOI or GOI substrates.

It should be noticed that the optimal device layers for light emission can also be fabricated on substrates without CMOS devices, resulting is in a far simpler and lower cost process flow. Some applications, such as Solid State Lighting (SSL), do not require the monolithic integration of the advanced epitaxial layers with CMOS. In this case there are three options: (1) fabricate single large ALED/Lixel device, (2) fabricate 2-dimensional array of ALED/Lixel devices contacted in parallel, (3) fabricate 2-dimensional array of ALED/Lixel devices contacted individually through “passive matrix addressing”.

The process flow disclosed in WO2002/33755 is an example in which it is assumed that the thermal budget required for the epitaxial deposition of the SiGeC layers is sufficiently low to be performed after the formation of the highly-doped source/drain regions for deep submicron (e.g. 0.18 μm) CMOS technologies. Low temperature epitaxial deposition processes (including the pre-epitaxy surface preparation) have been demonstrated. However, the most commonly used processes in production still require some-what larger thermal budgets to achieve the required films.

If the thermal budget for the epitaxial deposition of the SiGeC film is considered too high, then the deposition step could be inserted before the formation of the source/drain junctions. The thermal budget for epitaxial deposition of SiGeC films has been decreasing over time. It is widely acknowledged that there is a tendency towards lower thermal budgets, for this and many other process steps. It is reasonable to expect that at some time in the near future, production grade equipment and recipes will be compatible with the insertion of the epitaxial deposition step after the formation of the source/drain regions. Changing the substrate from silicon to germanium for CMOS technologies below 45 nm would further help decreasing the thermal budget because the germanium native oxide is very easily removed (it is water soluble), compared to the very stable silicon oxide. Therefore it is to be expected that germanium substrates/surfaces will enable multiple epitaxial deposition steps without impacting pre-existing doping/heterojunction profiles.

In the process flows described below, the “Isolation Module” can be conventional LOCOS or STI technologies, but STI will be the preferred one. Also, the “Ion Implantation Modules”, as well as the “Silicide Modules”, refer to the respective conventional process modules/steps/recipes.

In the following process flows, the details of materials, doping and heterojunction profiles, are not shown, because they are not needed for the description of the process flow, and because the process flow does not change if the details of those layers are changed.

The following is the list of layers/materials referenced in the Figures:

-   100—p-substrate -   101—active area -   102—STI -   103—p-well -   104—n-well -   105—p-type doped regions (105), isolating adjacent photo-diode     active areas -   106—n-type doped active area for epitaxial layers of APDs/ALEDs. -   107—Gate Insulator of MOSFET -   108—NMOS LDDs -   109—Highly n-type doped region, such as NMOS Source/Drain regions     (HDD) -   110—Field Isolation of Thin-Film SOI -   111—Gate electrodes -   12—Nitride spacers -   113—Deep Trench Isolation (DTI) -   114—Nitride film as hard mask for epitaxy -   115—Silicide -   116—Pre-Metal Dielectric -   117—Epitaxially deposited films—single crystal material over active     areas -   118—Epitaxially deposited films amorphous/poly-crystalline material     over field isolation areas -   120—Buried oxide of SOI substrates -   121—SOI mechanical substrate -   126—Light blocking layer -   127—Red color filter -   128—Green color filter -   129—Blue Color filter -   130—Contacts -   131—Metal-1 -   140—N-type doped region -   150—Transparent substrate -   151—N-type silicon substrate -   152—Back-side metallization -   160—P-type electrode and light emitting layer -   161—N-type electrode light emitting layer -   162—Acceleration region for front-side light emission -   163—Acceleration region for back-side light emission -   164—Filtering region for front-side light emission -   165—Filtering region for back-side light emission -   166—P-type electrode     Exemplary Process Flow #1

Fabrication of multiple ALED/Lixel devices contacted individually through “active matrix addressing”, made on a bulk substrate with a process flow for monolithic integration with CMOS devices. This exemplary process flow makes use of a twin-well process on a p-substrate silicon wafer. The flow described below indicates only the most important process modules.

Sequence of Process Modules (FIGS. 9A to 9H):

“Isolation Module”

“P-Well Implant Module”

“N-Well Implant Module” (FIG. 9A)

“Poly-Gate Module” (FIG. 9B)

“NMOS LDD Implant Module”

“PMOS LDD Implant Module”

“Lixel Implant Module” (FIG. 9C)

“Nitride Spacer Module”

“NMOS HDD Implant Module” (FIG. 9D)

“Pre-Epitaxy Module” (FIG. 9E)

A. Deposition of Si₃N₄ to be used as a hard mask for epitaxy;

B. Photolithography defining the windows where the epitaxial films are to be grown;

C. Etch to open windows over the active areas onto which epitaxial layers will be grown;

D. Photoresist strip and clean;

“Epitaxy Module” (FIG. 9F)

A. Pre-epitaxy clean;

B. Epitaxial growth of the layers with optimized doping and heterojunction profiles. The epitaxial growth can be selective or non-selective. The figure shows a non-selective growth;

C. Photolithography defining where the epitaxial films are to be removed;

D. Etch to remove epitaxial layers, stopping on the Si₃N₄ film underneath;

E. Photoresist strip and clean;

“Silicide Module” (FIG. 9G)

Formation of silicide with conventional methods/recipes:

A. Deposition of Si₃N₄ to be used as a hard mask for silicide formation;

B. Photolithography defining the windows where a silicide is to be formed;

C. Etch to open windows over the active areas in which a silicide will be formed;

D. Photoresist strip and clean;

E. Deposition (for example by sputtering) of a metal film;

F. Thermal annealing to form a silicide

G. Removal (for example, selective wet etch) of unreacted metal;

“Metallization Module” (FIG. 9H)

The metallization technology to be used can be the same used in standard CMOS technology. The thickness of the epitaxial layers, if it exceeds the typical thickness of the poly silicon gates of a given CMOS technology, might require some fine tuning of the planarization before forming contacts and metal-1 lines.

Exemplary Process Flow #2

Fabrication of multiple ALED/Lixels devices contacted individually through “passive matrix addressing”, made on a bulk substrate with a process flow simpler than the one required for monolithic integration with CMOS devices. This exemplary process flow makes use of p-substrate silicon wafers, and skips many steps used to fabricate standard CMOS devices.

Sequence of Process Modules (FIGS. 10A to 10E):

“Isolation Module”

“Ion Implantation Module” (FIG. 10A)

This module defines the locations to be ion implanted with n-type dopants.

In a preferred embodiment, there are three separate patterned ion implantation steps.

A first implant is the standard N-Well implant in CMOS processes, overlapping active areas and isolation regions.

A second implant into the active areas, will create doping levels similar to those used at the collector region of high-speed HBT devices in BiCMOS process. The second implant overlaps the N-Well implant along pre-determined regions.

A third implant overlaps the N-Well implant along pre-determined regions, and provides high dopant concentration in pre-defined surface regions.

“Pre-Epitaxy Module” (FIG. 10B)

A. Deposition of Si₃N₄ to be used as a hard mask for epitaxy;

B. Photolithography defining the windows where the epitaxial films are to be grown;

C. Etch to open windows over the active areas onto which epitaxial layers will be grown;

D. Photoresist strip and clean;

“Epitaxy Module” (FIG. 10C)

A. Pre-epitaxy clean;

B. Epitaxial growth of the layers with optimized doping and heterojunction profiles. The epitaxial growth can be selective or non-selective. The figure shows a non-selective growth;

C. Photolithography defining where the epitaxial films are to be removed;

D. Etch to remove epitaxial layers, stopping on the Si₃N₄ film underneath;

E. Photoresist strip and clean;

“Silicide Module” (FIG. 10D)

Formation of silicide with conventional methods/recipes:

A. Deposition of Si₃N₄ to be used as a hard mask for silicide formation;

B. Photolithography defining the windows where a silicide is to be formed;

C. Etch to open windows over the active areas in which a silicide will be formed;

D. Photoresist strip and clean;

E. Deposition (for example by sputtering) of a metal film;

F. Thermal annealing to form a silicide

G. Removal (for example, selective wet etch) of unreacted metal;

“Metallization Module” (FIG. 10E)

The metallization technology to be used can be the same used in standard CMOS technology. The thickness of the epitaxial layers, if it exceeds the typical thickness of the poly silicon gates of a given CMOS technology, might require some fine tuning of the planarization before forming contacts and metal-1 lines.

Exemplary Process Flow #3

Fabrication of multiple ALED/Lixel devices, all contacted simultaneously in parallel, made on a bulk substrate with a process flow simpler than the one required for monolithic integration with CMOS devices. This exemplary process flow makes use of n-substrate silicon wafers, and skips many steps used to fabricate standard CMOS devices. With this flow the contact to the bottom electrode is made through the back-side of the substrate, and that is why n-type substrate is used.

Sequence of Process Modules (FIGS. 11A to 11F):

“Isolation Module”

“Ion Implantation Module” (FIG. 11A)

With a n-type substrate, and contact to the bottom electrode being made through the back-side of the (thinned) wafer, there is no need for N-Well implant, nor for an implant to produce high n-type dopant concentration near the surface of the wafer.

Implant into the active areas, to create doping levels similar to those used at the collector region of high-speed HBT devices in BiCMOS process. The mask for this patterned implant overlaps the active areas in order to leave lower doping regions around the isolation regions.

“Pre-Epitaxy Module” (FIG. 11B)

A. Deposition of Si₃N₄ to be used as a hard mask for epitaxy;

B. Photolithography defining the windows where the epitaxial films are to be grown;

C. Etch to open windows over the active areas onto which epitaxial layers will be grown;

D. Photoresist strip and clean;

“Epitaxy Module” (FIG. 11C)

A. Pre-epitaxy clean;

B. Epitaxial growth of the layers with optimized doping and heterojunction profiles. The epitaxial growth can be selective or non-selective. The figure shows a non-selective growth;

C. Photolithography defining where the epitaxial films are to be removed;

D. Etch to remove epitaxial layers, stopping on the Si₃N₄ film underneath;

E. Photoresist strip and clean;

“Silicide Module” (FIG. 11D)

Formation of silicide with conventional methods/recipes:

A. Deposition of Si₃N₄ to be used as a hard mask for silicide formation;

B. Photolithography defining the windows where a silicide is to be formed;

C. Etch to open windows over the active areas in which a silicide will be formed;

D. Photoresist strip and clean;

E. Deposition (for example by sputtering) of a metal film;

F. Thermal annealing to form a silicide

G. Removal (for example, selective wet etch) of unreacted metal;

“Metallization Module” (FIG. 11E)

The metallization technology to be used can be the same used in standard CMOS technology. The thickness of the epitaxial layers, if it exceeds the typical thickness of the poly silicon gates of a given CMOS technology, might require some fine tuning of the planarization before forming contacts and metal-1 lines. In a typical application, the metallization module will have just one metal level.

“Back-Side Module” (FIG. 11F)

Deposition and annealing of a metal (for example aluminum) on the back-side of the wafer, to form the con-tact to the bottom electrode of the devices fabricated on the front-side of the wafer. Prior to the deposition of the metal on the back-side, the wafer is thinned to minimize the series resistance to the structures fabricated on the front side.

Exemplary Process Flow #4

Fabrication of multiple ALED/Lixels devices contacted individually through “active matrix addressing”, made on a Thin-Film SOI (or GOI) substrate with a process flow for monolithic integration with CMOS devices. The flow described below indicates only the most important process modules.

Sequence of Process Modules (FIGS. 12A to 12H):

“Isolation Module” (FIG. 12A)

“Poly-Gate Module” & “NMOS S/D Implant Module” (FIG. 12B)

“Pre-Epitaxy Module” (FIG. 12C)

A. Deposition of Si₃N₄ to be used as a hard mask for epitaxy;

B. Photolithography defining the windows where the epitaxial films are to be grown;

C. Etch to open windows over the active areas onto which epitaxial layers will be grown;

D. Photoresist strip and clean;

“Epitaxy Module” (FIG. 12D)

A. Pre-epitaxy clean;

B. Epitaxial growth of the layers with optimized doping and heterojunction profiles. The epitaxial growth can be selective or non-selective. The figure shows a non-selective growth;

C. Photolithography defining where the epitaxial films are to be removed;

D. Etch to remove epitaxial layers, stopping on the Si₃N₄ film underneath;

E. Photoresist strip and clean;

“Silicide Module” (FIG. 12E)

Formation of silicide with conventional methods/recipes:

A. Deposition of Si₃N₄ to be used as a hard mask for silicide formation;

B. Photolithography defining the windows where a silicide is to be formed;

C. Etch to open windows over the active areas in which a silicide will be formed;

D. Photoresist strip and clean;

E. Deposition (for example by sputtering) of a metal film;

F. Thermal annealing to form a silicide

G. Removal (for example, selective wet etch) of unreacted metal;

“Metallization Module” (FIG. 12F)

The metallization technology to be used can be the same used in standard CMOS technology. The thickness of the epitaxial layers, if it exceeds the typical thickness of the poly silicon gates of a given CMOS technology, might require some fine tuning of the planarization before forming contacts and metal-1 lines.

Optional “Backside Processing Module” (FIG. 12G)

After all processing has been done on the front-side of the substrate, there is an option to remove the back-side of the substrate. The buried oxide provides a marking layer for whatever method of removing the back-side is applied. Then the fully processed SOI (or GOI) layer can either:

(1) Be directly bonded to a new substrate, which can be light transparent or opaque, and can be an insulator or a conductor;

(2) Undergo processing on the newly exposed surface of the buried oxide, and then bonded to a new substrate.

Processing on the newly exposed surface of the buried oxide can be used for the purpose of:

(A) Electrical connections of structures made on the front-side of the wafer,

(B) Fabrication of additional electrical, and/or electronic, and/or optical, optoelectronic devices. Examples of such devices can be Antennas, vertical and/or horizontal Optical (half-) Cavities, Surface Plasmon-Polariton (SPP) structures such as “Light Funnels” (WO 2004/027879), etc. It should be noticed that the fabrication of an optical half-cavity on the back-side could be complemented with the fabrication of an half-cavity on the front side, immediately after the “Epitaxy Module”, and before the “Silicide Module”. (C) Fabrication of color filters, aligned with the photo-diodes fabricated on the front-side of the substrate, and light-blocking layer aligned with the transistors fabricated on the front-side of the substrate, as shown in FIG. 12G. 2. Types of Substrates and Epitaxial Layers

The method of fabrication of the present invention, can be implemented for different substrate materials (e.g., bulk silicon or germanium, Thick-Film SOI or GOI, Thin-Film SOI or GOI) and different orientations (<100>, <111>, etc.). Naturally there are differences with respect to the epitaxial films that can be grown on different materials and orientations, with consequences on the optoelectronic properties, and therefore on the performance and functionality.

It has been demonstrated that patterned areas of silicon substrates can be processed to achieve mono-layer flatness as demonstrated by S. Tanaka, G. C. Umbach, J. M. Blakely, R. M. Tromp, M. Mankos, “Fabrication of arrays of large step-free regions on Si(001)”, Appl. Phys. Lett, Vol. 69, No. 9, pp. 1235, 26 Aug. 1996, and D. Lee, J. Blakely, “Formation and stability of large step-free areas on Si(001) and Si(111)”, Surf Sci. Vol. 445, pp. 32, 2000; which is the ideal surface for the epitaxial growth of high quality pseudomorphic random alloys and short period superlattices. The processing required to produce atomic mono-layer flat active areas is compatible with the process flows of WO2002/33755 and WO2004/027879, as well as the layouts of a co-pending application, so that the photonic active layers of the devices in the current disclosure can be fabricated on such surfaces.

Independently of substrate material and orientation, the ALEDs require a certain functionality from the active layers: a first electrode, an “acceleration” region, an optional “energy filtering region”, and an “impact ionization” or “avalanching” region which is also the second electrode. For example, for a device made on a n-well on a p-substrate, the bottom electrode is n-type, and the top electrode, is p-type. The “acceleration” and “energy filtering” regions can be undoped.

From these requirements it can be immediately inferred that devices made on thin-film SOI or GOI must have the “acceleration” to be a part of the epitaxial stack, while for devices made on bulk or thick-film SOI substrates, carriers can be accelerated in the substrate. With bulk or thick-film SOI substrates the “acceleration” region can also be epitaxially grown, which enables bandgap engineering through carefully designed heterojunction profiles, with many potential advantages over an “acceleration” region made in a single homogeneous material.

An “energy filtering” region for electrons and/or holes can be made with a superlattices, as shown by J. Martorell, D. W. L. Sprung and G. V. Morozov, “Design of electron band pass filters for electrically biased finite superlattices”, Phys. Rev. B 69, 115309, 2004. The purpose of building such layers into the epitaxial stack, just before the formation of the “avalanching” region (top electrode), is to restrict the flux of carriers into the “avalanching” layer, to only those with energy within a certain range. That energy range is chosen to be the one that provides the highest probability of generating a radiative transition inside the “avalanching” region. As a consequence, the flux of carriers with energy outside the ideal range is suppressed, thereby sharply decreasing the total current, thus decreasing the total power dissipation, and therefore significantly increasing the overall efficiency power efficiency.

Ideally, the “energy filtering” region performs in such a way that every single carrier that is able to cross it, causes an impact ionization event that results in the emission of a photon. In such a scenario, the efficiency of avalanche light emission from an indirect bandgap material would approach the efficiency of light emission by the recombination of thermal carriers in direct bandgap materials.

Thin-Film SOI or GOI substrates allow the design of ALEDs for back-side emission of photons with energy larger than the bandgap of the substrate (e.g., silicon or germanium). The buried oxide layer is a perfect marking layer for the removal of the silicon or germanium mechanical substrates, thus enabling processing directly on the back-side of the buried oxide, and subsequent bonding to a transparent substrate. One of the many possibilities enabled by back-side processing is the fabrication of optical cavities. This is particularly useful for vertical cavity emitting devices.

A conventional resonant optical cavity would typically require the fabrication of half-cavity on the front-side, and another half-cavity of the back-side of the light emitting layer. Newer concepts, employing Surface Plasmon Polaritons (SPPs), which require the fabrication of patterned thin films of noble metals that are not compatible with conventional CMOS layouts and/or processing, can be easily implemented on the back-side of these substrates, after finishing all CMOS-compatible processing on the front-side, as already disclosed in WO2004/027879.

FIG. 1A presents a configuration for monolithic integration, showing one N-MOSFET connecting to the bottom electrode of one photonic device, in which the “Acceleration” region is n-type and is in the bulk, while the p-type epitaxial layer is the region in which light emission through impact ionization takes place. The contact to the bottom electrode is made outside the active area, through the n-Well implant.

FIG. 1B shows a configuration which differs from that of FIG. 1A, in that the “Acceleration” region is epitaxially deposited on a highly n-type doped surface. The “Acceleration” region can be undoped or lowly doped.

FIG. 1C shows a configuration which differs from that of FIG. 1B, in that the “Acceleration” region is epitaxially deposited on a highly n-type doped surface, and an optional “energy filtering” region is placed between the “Acceleration” and the region in which light emission through impact ionization takes place. The “Acceleration” and the “Filtering” regions can be undoped or lowly doped.

FIG. 2A presents a configuration, which may or may not be monolithically integrated with CMOS, made on bulk substrates, showing one photonic device and the contacts to the top and bottom electrodes, in which the “Acceleration” region is n-type and is in bulk, while the p-type epitaxial layer is the region in which light emission through impact ionization takes place. The contact to the bottom electrode is made outside the active area through the n-well implant.

FIG. 2B shows a configuration which differs from that of FIG. 2A, in that the “Acceleration” region is epitaxially deposited on a highly n-type doped surface. The “Acceleration” region can be undoped or lowly doped.

FIG. 2C shows a configuration which differs from that of FIG. 2B, in that the “Acceleration” region is epitaxially deposited on a highly n-type doped surface, and an optional “energy filtering” region is placed between the “Acceleration” and the region in which light emission through impact ionization takes place. The “Acceleration” and the “Filtering” regions can be undoped or lowly doped.

FIG. 3B presents a configuration for monolithic integration on ultra-thin film SOI or GOI substrates, showing one N-MOSFET connecting to the bottom electrode of one photonic device, for front-side light emission without a “Filter” region. The “Accelerator” region, which can be undoped, can be deposited directly on the n-type active area, followed by the deposition of the p-type film for light emission by impact ionization.

FIG. 3A presents a configuration for monolithic integration on ultra-thin film SOI or GOI substrates, showing one N-MOSFET connecting to the bottom electrode of one photonic device, for front-side light emission with a “Filter” region. The “Accelerator” region, which can be undoped, can be deposited directly on the n-type active area, followed by the “Filter” layers, and the deposition of the p-type film for light emission by impact ionization.

FIG. 3D presents a configuration for monolithic integration on ultra-thin SOI or GOI substrates, showing one N-MOSFET connecting to the bottom electrode of one photonic device, for back-side light emission without a “Filter” region. The “Accelerator” region, which can be undoped, can be deposited directly on the n-type active area or the N-type light emitting layer 161 as shown in FIG. 3D followed by the deposition of the p-type film for the p-type electrode 166.

FIG. 3C presents a configuration for monolithic integration on ultra-thin SOI or GOI substrates, showing one N-MOSFET connecting to the bottom electrode of one photonic device, for back-side light emission with a “Filter” region. The “Accelerator” region, which can be undoped, can be deposited directly on the n-type active area or the filter region for back-side light emission the N-type light emitting layer 165 as shown in FIG. 3C followed by the “Filter” layers, and the deposition of the p-type film for the p-type electrode 166.

FIG. 4B presents a configuration, which may or may not, be monolithically integrated with CMOS, made on ultra-thin film SOI or GOI substrates, showing one photonic device and the contacts to the top and bottom electrodes, for front-side light emission without a “Filter” region. The “Accelerator” region, which can be undoped, can be deposited directly on the n-type active area, followed by the deposition of the p-type film for light emission by impact ionization.

FIG. 4A presents a configuration, which may or may not be monolithically integrated with CMOS, made on ultra-thin film SOI or GOI substrates, showing one photonic device and the contacts to the top and bottom electrodes, for front-side light emission with a “Filter” region. The “Accelerator” region, which can be undoped, can be deposited directly on the n-type active area, followed by the “Filter” layers, and the deposition of the p-type film for light emission by impact ionization.

FIG. 4D presents a configuration, which may or may not be monolithically integrated with CMOS, made on ultra-thin SOI or GOI substrates, showing one photonic device and the contacts to the top and bottom electrodes, for back-side light emission without a “Filter” region. The “Accelerator” region, which can be undoped, can be deposited directly on the n-type active area or the N-type light emitting layer 161 as shown in FIG. 4D, followed by the deposition of the p-type film for the p-type electrode 166.

FIG. 4C presents a configuration, which may or may not be monolithically integrated with CMOS, made on ultra-thin SOI or GOI substrates, showing one photonic device and the contacts to the top and bottom electrodes, for back-side light emission with a “Filter” region. The “Accelerator” region, which can be undoped, can be deposited directly on the n-type active area or the filter region for back-side light emission the N-type light emitting layer 165 as shown in FIG. 4C, followed by the “Filter” layers, and the deposition of the p-type film for the p-type electrode 166.

3. Device “Active Layers”

As already described in the previous section, there are several groups of “active layers”. The bottom electrode, the “acceleration” region, the optional “energy filtering” region, and the “avalanching” region, which is the region in which light emission through impact ionization takes place, and that can be simultaneously the top electrode.

It is in the “acceleration” region that thermal carriers gain the necessary energy to successfully cause impact ionization in an adjacent “avalanching” region. The ability to gain energy from the electric field in the “acceleration” region depends on the electron and/or hole mobility in that region: the higher the mobility the larger the number of carriers acquiring the desired energy level to cause impact ionization. Therefore, it is highly advantageous for the “acceleration” region to be an undoped or lowly doped, single-crystalline region. The acceleration region can be designed to be part of the substrate of bulk wafers or thick-film SOI substrates, or can be epitaxially grown on any type of substrate: bulk, thick-film SOI, or thin-film SOI or GOI. With an epitaxially grown “acceleration” region, it is also possible to have sophisticated heterojunction and or doping profiles to enhance performance and/or functionality.

The optional “energy filtering” region, if implemented with a superlattice, requires single crystal epitaxial films with heterojunction engineering at the mono-layer level. Therefore this optional set of device layers must be epitaxially grown, regardless of the type of substrate.

In a preferred implementation, the “avalanching” region is also a single crystalline film with sophisticated heterojunction and doping profiles. However, it may also be a non-pseudomorphic film (alloys and/or superlattices), such as poly-crystalline, nano-crystalline, amorphous, or porous, of any of the materials listed below, and that can be formed on the silicon or germanium substrates.

The following subsections of the present disclosure provide more detailed information about different classes of materials/layers that can be used as the light emitting layer.

3.1. Epitaxial Layers Using Only Group IV Elements (C, Si, Ge, Sn) on Si Substrates

For reasons mentioned earlier, an exemplary implementation for monolithic integration with current state of the art CMOS technology is straightforward with random alloys and/or superlattices of pseudomorphic Si_(1-y)Ge_(x), and/or Si_(1-y)C_(y), and/or Si_(1-x-y)Ge_(x)C_(y), and/or Ge_(1-x)C_(x), strained to Si substrates, with any of the more relevant crystal orientations, such as (100), (111), or (311) for example.

The integration of random alloys and/or superlattices of pseudomorphic Si_(1-x)Ge_(x), and/or Si_(1-y)C_(y), and/or Si_(1-x-y)Ge_(x)C_(y), or and/or Ge_(1-z)C_(z), strained to Si substrates, and their incorporation into a device design in which light emission due to avalanche takes place inside those films/materials, enables performance and functionality gains that are more significant than a slight improvement upon pure silicon devices. The reason for a qualitative jump in performance, such as increased efficiency of radiative transitions, as well as functionality by the selection of preferential range of wave-lengths, is related to the qualitative differences between the band structure of silicon and germanium, and their combinations into random alloys and superlattices.

While in silicon the difference in energy between the indirect bandgap (1.1 eV) and the lowest direct bandgap (3.2 eV) is 2.1 eV, in germanium the difference between the indirect bandgap (0.66 eV) and the smallest direct bandgap (0.8 eV) is only 0.14 eV. For germanium, it is only necessary to add 0.14 eV of kinetic energy to the thermal electrons in the L-valley (along the <111> direction) to enable them to move into the F-valley, and thus enable highly efficient direct radiative transitions, by emitting 1.55 μm wavelength (0.8 eV) photons. Therefore, a region in which light emission by avalanching takes place, that is made of germanium rather than silicon, still has an indirect bandgap, but the consequences for optoelectronic interband transitions are more complex than simply taking the physical picture of the indirect bandgap of silicon and reduce it from 1.1 eV to 0.66 eV.

For the compositions of SiGe and/or SiGeC random alloys, used with current technologies, the bandgap structure is very similar to that of silicon's, including the big difference between the indirect and smallest direct bandgaps. However, that is not the case with SiGe/Si superlattices, in which “zone folding” radically changes the band structure along the axis of growth of the superlattice, as explained by M. J. Shaw and M. Jaros: “Fundamental Physics of Strained layer GeSi: Quo Vadis”, Chapter 4 of “Germanium Silicon: Physics and Materials”, Vol. 56, Academic Press, 1999. The impact of strain, and the impact of the superlattice period on the band structure have been theoretically and experimentally studied for the purpose of light detection and emission.

One of the most promising superlattices seemed to be Si₅—Ge₅ strained to a virtual substrate of relaxed Si₀₅Ge₀₅ random alloy. This particular superlattice is not suitable for monolithic integration with CMOS due to the required virtual substrate. Other superlattice designs that may result in a similar direct bandgap structure can be formed directly on the silicon substrate. One such superlattice consists of five mono-layers of Si_(1-y)C_(y) random alloy, with a large percentage of carbon, alternating with five mono-layers of pure Ge or Ge_(1-z)C_(z) random alloy. The amount of carbon in the Ge_(1-z)C_(z) layer can be varied depending on the goals to be achieved. Ge_(1-z)C_(z) alloys strained to Si have been demonstrated by M. Todd, J. Kouvetakis, D. J. Smith, “Synthesis and characterization of heteroepitaxial diamond-structured Ge_(1-x)C_(x)(x=1.5-5.0%) alloys using chemical vapor deposition”, Appl. Phys. Lett., Vol. 68, No. 17, 22 Apr. 1996, pp. 2407-2409; for much higher Carbon content, and for much thicker than the ones envisaged as required for this superlattice.

The effect of carbon on the band-structure of Germanium strained to the silicon lattice is not well characterized. What follows assumes that the addition of small amounts of carbon to a pure germanium film, will not result in qualitative changes, nor in dramatic quantitative changes to the band structure of the germanium film. It is also assumed that very small amounts of carbon can increase the critical thickness of nearly pure germanium layers strained to silicon substrates of any of the technologically relevant crystalline orientations.

Estimations indicate that the critical thickness for pure Ge on Si(100) is 1.2 nm. The incorporation of small amounts of carbon into the Ge layer can increase its critical thickness and enable the fabrication of SLs with larger number of monolayers of Ge (actually Ge_(1-z)C_(z)). Depending on the carbon content of both components of the (Si_(1-y)C_(y))₅—(Ge_(1-z)C_(z))₅ superlattice, it is possible for the overall layer stack to be strain compensated. It is possible to make the compressive strain in the (Si_(1-y)C_(y))₅ layer to be even larger than the tensile strain in the (Ge_(1-z)C_(z))₅ layer.

To have a pseudo-direct bandgap miniband, it is desirable to have a split in the conduction band of the silicon-rich layer—see for example F. Cerdeira: “Optical Properties”, Chapter 5, page 231 of “Germanium Silicon: Physics and Materials”, Vol. 56, Academic Press, 1999. Si tensile strained layers can be accomplished by growing silicon on a relaxed SiGe buffer layer (virtual substrate), or by including carbon in the layer: Si_(1-y)C_(y) strained to a Si substrate, as demonstrated by K. Eberl, K. Brunner, 0. G. Schmidt, “Si_(1-y)C_(y) and Si_(1-x-y)Ge_(x)C_(y) Alloy Layers” Chapter 8 of “Germanium Silicon: Physics and Materials”, Vol. 56, Academic Press, 1999. FIG. 2 (pp. 389) and 13 (pp. 403) of same book. FIGS. 16 (pp. 406) and 17 (pp. 407) show the band edge and bandgap of Si_(1-y)C_(y) strained to Si.

In the Si_(s)Ge_(s) superlattice strained to a virtual substrate of relaxed Si_(0.5)Ge_(0.5) random alloy, that split is induced by the tensile strain, which causes the four in-plane plane 4-valleys (Δ_(∥)) to be lifted (with respect to a bulk substrate), leaving unchanged the two Δ-valleys (Δ_(⊥)) along the direction of growth of the superlattice. In the (Si_(1-y)C_(y))₅—(Ge_(1-z)C_(z))₅ superlattice strained to the silicon lattice, the split in the conduction band of the silicon-rich layer is induced by the compressive strain caused by the presence of carbon in that film. The compressive strain causes the two Δ-valleys (Δ_(⊥)) along the direction of growth of the superlattice to be lowered with respect to a bulk substrate and the in-plane four Δ-valleys (Δ_(∥)).

The (Si_(1-y)C_(y))₅—(Ge_(1-z)C_(z))₅ superlattice is likely to have a very large “oscillator strength”, similar to that of Si₅—Ge₅ strained to a relaxed Si_(0.5)Ge_(0.5) random alloy. The (Si_(1-y)C_(y))₅—(Ge_(1-z)C_(z))₅ superlattice does not have to be strain compensated, but if it were, its total thickness would not be limited by strain.

Theory predicts that the top of the valence band of the SL originates in the bulk-Ge Γ-point states. Therefore replacing pure Ge with Ge_(1-z)C_(z) should increase the bandgap of the SL, because reduction in the strain of the Ge layer results in a smaller offset in the valence band with respect to the Si bulk. Therefore, there are good reasons to expect that a (Ge_(1-z)C_(z))_(m)—(Si_(1-y)C_(y))_(n) superlattice (for example with m=n=5) strained to a silicon substrate, should result in a pseudo-direct bandgap, with a high oscillator strength. The amount of carbon in the Si-rich layer controls the conduction band edge of the SL, and the amount of carbon in the Ge-rich layer controls the valence band edge of the SL. Therefore, through the modulation of the carbon content in both layers of the SL, it is possible to perform bandgap engineering of the SL layers.

The fact that the SL conduction band edge is lower in the direction of growth than laterally may have profound consequences for electron transport: the conduction band edge (potential energy) is lower for the direction perpendicular to the substrate, than for the directions parallel to the substrate. This anisotropy is likely to have very important consequences for scattering events, such as impact ionization, in particular for the angular distribution of the velocity of the generated electron-hole pairs.

The probability of recombination across the direct bandgaps in any of these materials can be further increased by heavy n-type doping in these layers. One reason is that the lowest states in the conduction band are occupied by electrons from the heavy doping, thus pushing the Fermi-Level towards the direct bandgap edge of the conduction band. This is especially relevant to indirect bandgap films/materials in which said direct bandgap is not much larger than the lowest indirect bandgap, such as germanium and superlattices containing Si, Ge, C, in which the pseudo-direct bandgap is only slightly larger than the lowest indirect bandgap.

The highest in-situ doping level possible might be achieved by incorporating impurities of several species, rather than just one as it is normally done. For example the epitaxial of Si, SiGe, SiGeC, Ge films process could have gases carrying the three commonly used n-type dopants: P, As, Sb. Very heavy doping means that there is a significant percentage of foreign atoms in the crystalline lattice. Germanium atom concentration is 4.42×10²² cm⁻³. A doping concentration of for example, 5×10^(2°) cm⁻³ represents more than 1% of the atoms in the lattice. It should be kept in mind that in many SiGeC films, the carbon concentration is below 1%, and still there are important chemical and strain effects from carbon in those films. Another consequence of heavy doping is “Band Gap Narrowing” (BGN).

This effect is detrimental for certain devices such as solar cells, but it can be an advantage for the devices of the present invention.

In conventional homojunction or heterojunction interband light emitting diodes, radiative recombination takes place in a region separating a p-type and n-type regions that act as hole and electron injectors, respectively. In homojunction devices this region is simply the depletion region. In heterojunction devices this region is chosen to have a narrower bandgap, and have a type-II alignment with respect to the p-type and n-type doped regions, thereby confining electrons and holes.

In the present invention some implementations depart from this conventional device architecture, and the region in which radiative recombination is to take place is the heavily n-type doped region.

FIGS. 5, 6, 7, and 8 show device layer profiles, in which the doping and heterojunction profiles are such that light emission through impact ionization takes place in a highly n-type doped region.

FIG. 5 shows a qualitative band diagram of a device with a p-type silicon bottom electrode, an undoped silicon “Accelerator” region, and n-type doped Ge layer, capped by a thin silicon layer, also n-type doped.

FIG. 6 shows a qualitative band diagram of a device with a p-type silicon bottom electrode, an undoped silicon “Accelerator” region, and n-type doped (SiC)—(GeC) superlattice layers, capped by a thin silicon layer, also n-type doped.

FIG. 7 shows a qualitative band diagram of a device with a p-type silicon bottom electrode, an undoped SiGe or SiGeC “Accelerator” region, and n-type doped light emitting layer, capped by a thin silicon layer, also n-type doped. At the interface of the “Accelerator” region with the n-type doped light emitting layer, there is a conduction band offset. That offset can be used as an energy filter, in the sense that only carriers with kinetic energy (along the direction perpendicular to the substrate) above the barrier reach the n-type doped layer. The barrier should be thin enough so that carriers cross it without scattering, but thick enough to prevent tunneling. This barrier should prevent thermal carriers from reaching the n-type doped layer, and therefore suppresses a large portion of current that would not induce impact ionization on the n-type doped layer.

In the devices of FIGS. 5, 6, and 7, free holes are injected into the heavy n-type doped region Electron-hole pair generation by impact ionization inside the n-type region. This requires the existence of an “acceleration” region in which carriers gain energy from an electric field.

Since in silicon and germanium electron mobility is significantly higher than hole mobility, it is advantageous to design devices in which impact ionization is caused by hot electrons, rather than hot holes. Therefore, devices should be designed for light emission through avalanche of hot electrons. However in superlattice acceleration regions this may not be the case, and it may happen that it is more advantageous to have light emission from impact ionization by hot holes.

FIG. 8 shows an exemplary qualitative band diagram of a device under forward bias, rather than reverse avalanche bias. This device shows that with a conduction band barrier at the n-type doped light emitter and the middle layer (in this case not really an “accelerator”), it is possible to inject electrons into the n-type doped light emitter, and to prevent them from moving towards the substrate. The device of FIG. 8 should have a direct band-gap n-type layer, because the recombinations in that layer are between thermal electrons and thermal holes.

3.2. Implementation Using Pure Ge and/or Ge_(1-z)C_(z) Random Alloys on Si Substrates

With very heavy n-type doping, the Fermi level may be positioned well above the lowest conduction band edge, which makes the lower energy states in the L-valley of the conduction band of germanium to be fully occupied. The deeper the Fermi level is inside the conduction band of germanium, the smaller the energy necessary to make electrons populate the bottom of the Γ-valley. With high enough n-type doping, it could be possible to position the Fermi level above the bottom of the Γ-valley. In that situation direct optoelectronic transitions across the bandgap become possible even with thermal electrons, provided that free holes are available to recombine with those electrons.

3.3. Implementation Using (Si_(1-y)C_(y))_(m)—(Ge_(1-z)C_(z))_(n) Superlattices on Si Substrates

Heavy n-type doping effects can also be exploited in the minibands of (Si_(1-y)C_(y))₅—(Ge_(1-z)C_(z))₅ superlattices, in the same way that it is for pure Ge films. If the lowest interband transition is indirect, but that a direct transition is within a very short distance (in energy), then that difference can be partially or totally bridged with heavy n-type doping, i.e., the Fermi level can be positioned very close or even above the F-valley of the conduction miniband, and thus the F-valley can be populated with thermal electrons. Radiative recombination leads to the emission of photons with energy corresponding to the difference between the top of the valence band and the Fermi level inside the conduction band. Such high concentration of impurities may result in increased band mixing and charge carrier scattering, which could be advantageous to increase the oscillator strength of direct transitions across the gap of the miniband.

3.4. Implementation Using Si₂Sn₂C and/or Ge₃SnC on Si Substrates

As mentioned before, these random alloys have direct bandgaps, and therefore do not require heavy n-type doping of the active region, nor avalanching to bring electrons to the F-valley to make efficient radiative recombinations possible. Information about these materials as provided by P. Zhang, V. H. Crespi, E. Chang, S. G. Louie, M. L. Cohen, “Theory of metastable group-IV alloys from CVD precursors”, Phys. Rev. B, Vol. 64, pp. 235201, 2001; leads to the expectation that they can be incorporated into devices for light emission and light detection, including APDs and ALEDs, and that can be monolithically integrated with sub-100 nm CMOS as disclosed in the present invention. Their bandgaps are direct and small (0.625 eV for Si₂Sn₂C and 0.312 eV for Ge₃SnC) compared to silicon, thus opening new possibilities for detection in the Mid-Wavelength Infra-Red (MWIR). It is also possible to combine these two materials into superlattices, and vary the bandgap continuously between 0.312 eV and 0.625 eV. In addition it is also possible to make superlattices of Si₂Sn₂C (and/or Ge₃SnC and Si, SiGe, SiGeC etc. At the moment the band structures of such materials are not known.

3.5. Implementation Using Amorphous Si, Ge, SiGe Light Emitting Layers

This approach attempts to combine the best possible aspects of the crystalline silicon for being the acceleration region, in which mobility is critical, and the avalanching layer, which does not need to have a high mobility. In fact it is useful to have a high probability of impact ionization, thus scattering, which is typical of non-single-crystal materials, and which is helped by heavy doping.

As mentioned before, the layers in which light emission through impact ionization takes place, might not be single crystalline, but rather, a thin film, for example less than 20 nm, of a-Si, or a-Ge, or a-SiGe. The amorphous layers, should be heavily doped to maximize the probability of scattering and impact ionization. Carriers accelerated in the underlying crystalline CMOS layers, will undergo impact ionization the moment they enter these heavily doped amorphous layers.

Amorphous layers are interesting because their thickness is not restricted by strain, and because amorphous layers have modified band structures with respect to the single crystalline form of the same material: for example a-Si has a direct bandgap that is slightly larger than that of c-Si.

3.6. Devices Using Non-Group IV Elements on Silicon Substrates

As mentioned earlier, there a few direct bandgap materials, that have been epitaxially grown on silicon, but that are not made of Group-IV components: CuIn_(1-x)Ga_(x)S₂ with bandgap varying linearly with Ga content from 1.5 eV (x=0) to 2.5 eV (x=1) as demonstrated by H. Metzner, J. Cieslak, J. Eberhardt, Th. Hahn, M. Müller, U. Kaiser, A. Chuvilin, U. Reislöhner, and W. Witthuhn, R. Goldhahn and F. Hudert, J. Kräußlich, “Epitaxial CuIn_(1-x)Ga_(x)S₂ on S(111): A perfectly lattice-matched system for x≈0.5”; Appl. Phys. Lett., Vol. 83, No. 8, 25 Aug. 2003, pp. 1563-1565, and SiCAlN with a 3.2 eV bandgap as demonstrated by John Tolle, R. Roucka, P. A. Crozier, A. V. G Chizmeshya, I. S. T. Tsong, and J. Kouvetaki s, “Growth of SiCAlN on Si(111) via a crystalline oxide interface”, Appl. Phys. Lett., Vol. 81, No. 12, 16 Sep. 2002, pp. 2181-2183.

GaSe, has been experimentally demonstrated by Reiner Rudolph, Christian Pettenkofer, Aaron A. Bostwick, Jonathan A. Adams, Fumio Ohuchi, Marjorie A. Olmstead, Bengt Jaeckel, Andreas Klein, and Wolfram Jaegermann, “Electronic structure of the Si(111):GaSe van der Waals-like surface termination”, New Journal of Physics 7 (2005)108; to be epitaxially compatible, and having an interface with (111) silicon, in which there are no energy levels in the gap of silicon. The same has been found to be true for AlSe by J. A. Adams, A. Bostwick, T. Ohta, Fumio S. Ohuchi, and Marjorie A. Olmstead, “Heterointerface formation of aluminum selenide with silicon: Electronic and atomic structure of Si(111):AlSe”, Phys. Rev. B 71, 195308 2005. Both these materials have bandgaps larger than silicon, thus allowing for the modification of the wavelength of emission.

Iron-Silicide (β-FeSi₂) has been identified as a direct bandgap semiconductor that can be formed on silicon, potentially compatible with CMOS, and that has a bandgap suitable for light emission and absorption of the wavelength bands relevant to fiber optics telecommunications. However until now light experimental emission from this material has not met the high expectations regarding efficiency. The attempts done so far rely on conventional designs for light emitting devices, such as those by M. Takauji, C. Li, T. Suemasu, and F. Hasegawa, “Fabrication of p-Si/β-FeSi₂/n-Si Double-Heterostructure Light-Emitting Diode by Molecular Beam Epitaxy”, Jpn. J. Appl. Phys., Vol. 44, No. 4B, 2005, pp. 2483-2486.

The present invention enables the utilization of this material within a device design in which the light emission takes place by interband transitions induced by impact ionization inside this material. Its insertion in the CMOS process flow follows the guidelines devised for SiGeC films, including the p-type doping by Boron as identified by Y Terai, Maeda, “Enhancement of 1.54 μm photoluminescence observed in Al-doped β-FeSi₂”, Appl. Phys. Lett., Vol. 84, No. 6, 9 Feb. 2004, pp. 903-905. It can also be used with bulk, thick-film SOI, thin-film SOI, and in conjunction with “energy filtering” layers.

The design superlattices incorporating some these materials, CuIn_(1-x)Ga_(x)S₂, SiCAlN, GaSe, AlSe, β-FeSi₂, Si₂Sn₂C and Ge₃SnC, should allow the bandgap to be varied between 0.312 eV and 3.2 eV. With the present invention, it is possible to envision stacks of such layers for light emission and/or light absorption, each set of layers in the stack operating in a different wavelength or range of wavelengths, monolithically integrated with CMOS.

3.7. Devices Using Group IV Elements (Si, Ge, C, Sn) on Ge Substrates

This device and method of fabrication of the present invention is highly suitable to be applied to Ge substrates, such as bulk Ge and/or GOI, because of the 0.8 eV direct bandgap. One way to take advantage would be to have the avalanching region as heavily n-type doped as possible, because that would make low energy states unavailable to the hot electrons. The heavy n-type doping will fill up as many states as possible in the bottom of the conduction band of Ge or in the conduction mini band of a superlattice. Ideally all the states in the indirect band(s) would be completely filled up, so that external electric fields can inject electrons directly into the direct band(s). The heavier the doping and thus thermal electron population, the more likely it is that any hot electron relaxation is indeed across the 0.8 eV direct bandgap, rather than across the 0.66 eV indirect bandgap.

The smaller the energy difference between the Fermi-level in the indirect band and the bottom of the lowest lying direct band, the lower the energy that electrons need to gain in order to move into the direct band and thus have a very high probability of participating in radiative transitions. In this case it is possible that increasing the applied voltage, that is, increasing the maximum energy attainable by the electrons, results in an increase of the energy of the radiative transitions, thereby resulting in a “blue shift” of the photons emitted.

Additionally, using bulk Germanium or GOI substrates enables the growth epitaxial films containing Sn, and consequently enables radiative interband transitions emitting photons in the far infrared.

Due to the low processing temperature of germanium, and especially to the ease with which the surface of a germanium substrate can be cleaned and made ready for epitaxy, it is then straightforward to have more than one epitaxial growth, and it becomes possible to have multiple epitaxial devices, grown on adjacent active areas, with different materials and/or doping/heterojunction profiles, optimized for different wavelength ranges of the electromagnetic spectrum.

3.8. Implementation with Pure Ge Device on Ge-Based Substrates

As mentioned above, a pure Ge layer with heavy n-type doping can have the Fermi level very close or above the F-valley. This enables radiative direct transitions through the recombination of thermal electrons and holes. If the heaviest possible n-type doping not be enough to bring the Fermi level close enough to edge of the F-valley, then radiative direct transitions between electrons in the F-valley and holes at the top of the valence band can still take place by populating the F-valley with hot electrons. As also mentioned earlier this is easily achieved with a device architecture in which impact ionization takes place inside the heavy n-type doped layer.

3.9. Implementation Using Group IV Elements on Ge-Based Substrates

Some GeSn alloys have been shown by M. R. Bauer, C. S. Cook, P. Aella, J. Tolle, and J. Kouvetakis, P. A. Crozier, A. V. G. Chizmeshya, and D. J. Smith, S. Zollner, “SnGe superstructure materials for Si-based infrared optoelectronics”, Appl. Phys. Lett., Vol. 83, No. 17, 27 Oct. 2003, pp. 3489-3491; by H. Perez Ladrön de Guevara, A. G. Rodriguez, H. Navarro-Contreras, and M. A. Vidal, “Ge_(1-x)Sn_(x) alloys pseudomorphically grown on Ge(001)”, Appl. Phys. Lett., Vol. 83, No. 24, 15 Dec. 2003, pp. 4942-4944; and by G. He and H. A. Atwater, “interband Transitions in Sn_(x)Ge_(1-x) Alloys”, Phys. Rev. Lett., Vol. 79, No. 10, 8 Sep. 1997, pp. 1937-1940, have direct bandgaps; and some Ge/Sn superlattices have also been show by D. Munzar, and N. E. Christensen, “Electronic Structure of Sn/Ge superlattices”, Phys. Rev. B, Vol. 49, NO. 16, 15 Apr. 1994-11, pp. 11238-11247, Table V in page 11242, have direct bandgaps. Because Sn atoms are larger than Ge, it is also conceivable that Si and C atoms may be added for partial or total strain compensation, thereby enhancing the critical thickness. The following are examples of superlattices feasible to grow on germanium substrates: (Si_(1-y)Ge_(y))_(m)—(Ge_(1-z)Sn_(z))_(n); (Si_(1-y)Sn_(y))_(m)—(Ge_(1-z)Sn_(z))_(n); (Si_(1-y)C_(y))_(m)—(Ge_(1-z)Sn_(z))_(n); (Si_(1-y)Ge_(y))_(m)—(Sn_(1-z)C_(z))_(n); and (C_(1-y)Ge_(y))_(m)—(Ge_(1-z)Sn_(z))_(n).

3.10. Devices Using Non-Group IV Elements on Germanium Substrates

It has been long known that germanium is a good starting substrate for the epitaxial growth of GaAs films and devices. Naturally, the current invention can also incorporate such direct bandgap films. The films can have the conventional profiles for light emitting devices, or can also be engineered to be thin and highly doped for light emission through impact ionization in said films.

4. Application of ALEDs/Lixels

4.1. Solid-State Lighting (SSL)

ALEDs built with direct or pseudo-direct bandgap materials should have very high power efficiency, approaching that of conventional direct bandgap materials used for Solid-State Lighting. For this application, it would not be necessary to have a monolithic integration of the ALED devices with CMOS, and therefore the process flow would be much simpler and cheaper.

The advantages over conventional materials and devices for SSL would be many, starting with production costs several order of magnitude lower, especially when considering that ALEDs can be fabricated on standard 300 mm silicon substrates, with all the well established silicon process technologies and equipment, while the state of the art devices for SSL are made on 3″ or 4″ expensive substrates, such as sapphire.

4.2. Operation as Light Emitter or Light Absorber

The same device that has been described as a light emitter, when biased below the breakdown voltage can also be operated as an avalanche photo-detector. The exact same photonic layers (APD/ALED layers) that are part of the cells described in all Pixel/Lixel designs of a co-pending application can be operated as light sensors or light emitters. To be operated as an APD for light sensing, the voltage applied to the terminals of the APD/ALED must be below the break-down voltage. With the appropriate circuitry at the periphery of the sensor/emitter matrix, the total current flowing through the APD can be controlled to suit different conditions of illumination. To be operated as an ALED, for light emission, the voltage applied to the terminals of the APD/ALED must be equal or above the breakdown voltage. With the appropriate circuitry at the periphery of the matrix, the total current flowing through the ALED can be controlled to prevent dam-age to the device. A matrix of ALEDs can have different applications.

4.3. Application of ALEDs/Lixels for Displays

If the efficiency of light emission and electrical power dissipation are appropriate, a matrix of light emitting elements (Lixels) can be scaled to make displays with an “Active Matrix” (active addressing) of “Active Pixels/Lixels”, that is, a matrix in which each Pixel/Lixel emits light, and in which each pixel has its own turn on/off switch (a MOSFET device). Full color displays can be achieved by making a color filter mosaic, such as the Bayer pattern, which is identical to that used for color image sensing. The ability of making extremely small active pixels, compared to the usual Pixel/Lixel sizes of conventional flat panel displays, enables the fabrication of small displays with very high resolution, and thus very high image/video quality. The very small pixel size could be used to engineer display architectures in which a “Macro-Pixel/Lixel” for a particular primary color, is itself a matrix of many minimum-size Pixels/Lixels. This architecture makes possible to define the light intensity, and dynamic range, by the number of minimum-size Pixels/Lixels that are “ON” inside a Macro-Pixel/Lixel. For example, a Macro-Pixel/Lixel composed of a matrix of 256×256 minimum-size Pixels/Lixels can produce 256×256=65,536 levels of light intensity, which corresponds to a 16 bit dynamic range. This is a very conservative estimate because it assumes that each Pixel/Lixel can only be either “ON” or “OFF”. If each Pixel/Lixel could have 4 different levels of light intensity (corresponding to 4 different applied voltages), then the dynamic range would be 18 bit. At the moment, the best dynamic range for the most common flat panel display technologies, Plasma Displays and Liquid Crystal Displays are in the 10 to 12 bit range.

4.4. Application of Pixels/Lixels for a Dual-Mode Sensor/Emitter Matrix

A matrix of Pixels/Lixels, for sensing/emitting light can be used in a camera for video or still photography, with the ability to alternate (through software control) image acquisition and light emission. This alternate functionality can be used for the following applications:

3D-Imaging

The measurement of the “Time-Of-Flight” (TOF) between the emission of photons and the detection of the reflected photons can be used for 3-dimensional imaging. This includes the possibility to measure multiple reflections, and thus see “behind” the objects in the field of view. The measurement of the time of flight can be made with light emission/detection using only some or all of the primary colors. If only the IR is used, the image as seen by the human eye and recorded by typical cameras (film and digital), will not be disturbed. The fact that the light used for this purpose reaches the objects in the field of view through the lens of the camera (traveling in the opposite direction of the light that forms an image on the sensor) may have benefits in terms of power needed as well as better control of secondary reflections. This can be especially useful when using tele-photo lens to capture 3D images of very far away objects.

ALEDs/Lixels as a Fully Integrated Flash

In this case the light of the flash travels through the lenses of the camera, and illuminates directly only what is in the field of view of the lenses, regardless of their type (wide angle, macro, telephoto, etc.). In turn this should decrease the optical power requirements, compared to a conventional flash, which emits light isotropically. It is possible to control the color(s) and color temperature of the flash, by controlling the light intensity that goes through each type of primary color filter (R, G, B, IR). This is radically different from conventional flashes for cameras.

Monolithically Integrated Optoelectronic Transceiver

With appropriate the material/composition for the epitaxially deposited light emitting film, it is possible to have light absorption & emission in the infrared, namely in the 1.3 μm to 1.55 μm range, which are the wavelengths used in fiber optics communications. Therefore, it becomes possible to fabricate CMOS integrated circuits that can directly receive light signals from, and emit light signals to, optical fibers, thereby enabling low cost technology alternative to solutions based on III/V compound semiconductors.

In the present disclosure, several materials have been mentioned as good candidates to cover these wavelength ranges: (Ge_(1-z)C_(z))₅—(Si_(1-y)C_(y))₅, β-FeSi₂, Si₂Sn₂C, and Ge₃SnC. 

The invention claimed is:
 1. A device, comprising: a photonic device having multiple active layers arranged in a stack, the active layers including a charge carrier energy filtering layer between a charge carrier acceleration layer and an photonic layer that emits and absorbs light, the active layers being configured such that application of a voltage across the active layers controls emission and absorption of light from the photonic layer, the filtering layer preventing charge carriers with a first range of energy from reaching the light photonic layer from the accelerator layer while allowing charge carriers with a second range of energy to reach the light photonic layer from the accelerator layer, the active layers being configured such that recombination of the charge carriers with the second range of energy and momentum in the photonic layer produces the light emission from the photonic layer, the photonic layer includes an epitaxially deposited material selected from a group consisting of Si, Ge, a random alloy of Si, and a random alloy of Ge; and a CMOS device monolithically integrated with the photonic device, the CMOS device and the photonic device being on a substrate having an active region, at least one of the active layers being epitaxially deposited on the active region of the substrate.
 2. The device of claim 1, wherein the epitaxially deposited material is selected from a group consisting of Si_(1-z)Sn_(z), Ge_(1-y)C_(y), Ge_(1-z)Sn_(z), Ge_(1-y-z)C_(y)Sn_(z), Si_(1-x-y)Ge_(x)C_(y), and Si_(1-x-y-z)Ge_(x)C_(y)Sn_(z).
 3. The device of claim 1, wherein the photonic device is a diode.
 4. The device of claim 1, wherein the substrate is selected from a group consisting of bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, and Thin-Film GOI.
 5. The device of claim 1, wherein the epitaxially deposited material is positioned on the active region of the substrate.
 6. The device of claim 1, wherein the epitaxially deposited material has an indirect bandgap.
 7. The device of claim 1, wherein the photonic layer includes a superlattice.
 8. The device of claim 1, wherein the photonic layer is in direct contact with a component selected from a group consisting of the substrate and one of the active layers such that the photonic layer is pseudomorphic.
 9. A device, comprising: a photonic device having multiple active layers arranged in a stack, the active layers including a charge carrier energy filtering layer, an acceleration layer and a photonic layer that emits and absorbs light, the active layers being configured such that application of a voltage across the active layers controls emission of light from the photonic layer and absorption of the light by the photonic layer, the filtering layer preventing charge carriers with a first range of energy from reaching the light photonic layer from the accelerator layer while allowing charge carriers with a second range of energy to reach the light photonic layer from the accelerator layer, the active layers being configured such that recombination of the charge carriers with the second range of energy and momentum in the photonic layer produces the light emission from the photonic layer, the photonic layer includes an epitaxially deposited material selected from a group consisting of Si, Ge, a random alloy of Si, and a random alloy of Ge, the acceleration layer having a bandgap that is wider than a bandgap of the photonic layer, the photonic layer having a bandgap narrower than a bandgap of the acceleration layer, a capping layer on the photonic layer, the capping layer having a bandgap wider than the bandgap of the photonic layer, the capping layer providing conduction and valence band barriers; and a CMOS device monolithically integrated with the photonic device, the CMOS device and the photonic device being on a substrate.
 10. The device of claim 9, wherein the charge carrier energy filtering layer is between the acceleration layer and the photonic layer.
 11. The device of claim 9, wherein the epitaxially deposited material is selected from a group consisting of Si_(1-z)Sn_(z), Ge_(1-y)C_(y), Ge_(1-z)Sn_(z), Ge_(1-y-z)C_(y)Sn_(z), Si_(1-x-y)Ge_(x)C_(y), and Si_(1-x-y-z)Ge_(x)C_(y)Sn_(z).
 12. The device of claim 9, wherein the photonic device is a diode.
 13. The device of claim 9, wherein the substrate is selected from a group consisting of bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, and Thin-Film GOI.
 14. The device of claim 9, wherein the epitaxially deposited material is positioned on the active region of the substrate.
 15. The device of claim 9, wherein the photonic layer is p-type doped.
 16. The device of claim 9, wherein the epitaxially deposited material has an indirect bandgap.
 17. The device of claim 9, wherein the photonic layer includes a superlattice.
 18. The device of claim 9, wherein the photonic layer is in direct contact with a component selected from a group consisting of the substrate and one of the active layers such that the photonic layer is pseudomorphic. 